In a nonvolatile semiconductor memory device such as an NAND flash memory, as miniaturization of memory cells advances, a technology of combining a flat cell structure and a hybrid structure has attracted attention in place of a rocket structure having danger such as fall.
The flat cell structure has the advantage that a control gate electrode does not enter a space between charge storage layers arranged in a row direction in which the control gate electrodes (word lines) extend, and hence a half of a pitch (the half pitch) of bit lines extending in a column direction is not restricted.
Moreover, the hybrid structure can store a larger amount of charges in a charge trap layer by a charge storage layer comprising a floating gate layer on a semiconductor substrate side and the charge trap layer on a control gate electrode side. Consequently, the hybrid structure has the advantage that writing/erasing characteristics (a threshold value window) can sufficiently be acquired, even when the memory cells are miniaturized.
However, when the flat cell structure and the hybrid structure are combined, an element in the control gate electrodes diffuses in a high-permittivity insulating layer (a high-k material layer) and the charge storage layer by a heat treatment to activate a diffusion layer formed in the semiconductor substrate. In consequence, there has been the problem that the writing/erasing characteristics deteriorate.